Partial Reconfiguration Fpga Thesis

Many bus and network-on-chip (No C) architectures have been proposed to exploit this capability on FPGA technology.However, few realizations have been reported in the public literature to demonstrate or compare their performance in real world applications.

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It is found that a No C provides much better performance than a single channel bus and similar performance to a multi-channel bus in both parallel and parallel-pipelined FFT systems.

This suggests that a No C is a better choice for systems with multiple simultaneous communications like the FFT.

However, this brings drawbacks including resource utilization inefficiency, power consumption overhead and decrease in system operating frequency.

The experimental results report a 50% of resource utilization inefficiency with a power consumption overhead of less than 5% and a decrease in frequency of up to 32% compared to a static implementation.

We also applied decoupling strategy to isolate thereconfigurable modules during PR to avoid undesirable outcoming signals to affect the rest of thedesign.

Finally, we made an evaluation of our work and constructed a benchmark to show theacceleration advantages of PR.

In this benchmark, the system could adapt to computation requirementsand reconfigured idle peripherals with others that were needed, to distribute the computational loadbetween them and so, to reduce the total computation time.

Dynamically partially reconfigurable FPGAs (Field-Programmable Gate Arrays) allow hardware modules to be placed and removed at runtime while other parts of the system keep working.

While partial reconfiguration can offer many benefits, it is still rarely exploited in practical applications.

Few full realizations of partially reconfigurable systems in current FPGA technologies have been published.


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